Area Optimized Implementation For Mips Processor

Abstract

The implementation of 32 bit RISC processor with microprocessor without interlocked pipeline stages (MIPS) is presented. It was implemented in VHDL so as to reduce the instruction set present in the programmable memory. As the result the processor will contain the necessary logics for the implementation that requires fewer gates to be synthesized in the programmable matrix and has the capability to increase the speed of the target processor with reduced memory. In this paper we propose a novel technique of run-time loading of machine code for MIPS-32 soft-core processor. As we know, implementing fewer instructions on silicon reduces the complexity of the instruction decoder, the addressing logic, and the execution unit. This allows the machine to be clocked at a faster speed, since less work needs to be done each clock period. In this paper we used Xilinx- ISE tool for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and