Area Optimization of Slicing Floorplans in Parallel

Cheng-Hsi Chen,Ioannis G Tollis

doi:10.1155/1994/63707

Abstract

We first present a parallel algorithm for finding the optimal implementations for the modules of a slicing floorplan that respects a given slicing tree. The algorithm runs in O(n) time and requires O(n) processors, where n is the number of modules. It is based on a new O(n2) sequential algorithm for solving the above problem. We then present a parallel algorithm for finding a set of optimal implementations for a slicing floorplan whose corresponding slicing tree has height O(logn). This algorithm runs in O(n) time using O(logn) processors. Our parallel algorithms do not need shared memory and can be implemented in a distributed system.

Highlights

We first present a parallel algorithm for finding the optimal implementations for the modules of a slicing floorplan that respects a given slicing tree
The target of floorplanning is to partition the floor rectangle into smaller ones, called basic rectangles, and embed the basic modules into these small rectangles preserving the relative positions of the modules [7, 8]
We compared the number of steps needed for the sequential algorithm with the number of steps needed for the parallel algorithm

Summary

Introduction

We first present a parallel algorithm for finding the optimal implementations for the modules of a slicing floorplan that respects a given slicing tree. We present a parallel algorithm for finding a set of optimal implementations for a slicing floorplan whose corresponding slicing tree has height O(logn). This algorithm runs in O(n) time using O(logn) processors. Loorplan design is the first task in VLSI layout and perhaps the most important one It is the problem of allocating space to a set of modules on the chip in order to minimize the area of the chip. If each basic rectangle has c implementations, where c is a constant, there are O(c") possible sets of implementations for the floor rectangle

Methods

Results

Conclusion