Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop

Abstract

The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. The results reveal that for 16 bit CSA improvement of power delay product (PDP) of the proposed design using negative edge triggered D flip flop is 78% & 18% when compared to CSA with BEC and CSA with conventional D flip flop. When CSA implemented in a partitioned Dadda multiplier it results in performance improvement of 74 % with little increase in total power dissipation.