A high performance flip flop for low power low voltage systems

Abstract

The paper presents a new design for implementing a static Master-Slave Flip-flop with reduced transistor count for low power and high performance applications. The proposed flip-flop is realized using only eleven transistors (including an inverter to produce complementary clock signals locally) hence reducing the manufacturing cost. SPICE simulation results at a frequency of 250 MHz using 180 nm/1.8V CMOS Technology BSIM3v3 parameters indicate at least 16% improvement in power-delay product with respect to the conventional static Master-Slave flip flop configurations. The flip-flops have been analysed with due emphasis on operation at scaled power supply voltages. The proposed design shows an improvement of 46.04% in power-delay product at lower voltages.