Area and Power Efficient Array and Tree Multipliers

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New circuit implementations of the partial product generators (PP), for array and tree architectures, are presented in this paper. They require less number of transistors and consequently resulting in a smaller area and less power dissipation. The realization of 8times8 array multipliers based on our new low power low area PP implementations achieved 17% and 13.3% reduction in power consumption and transistor count respectively compared to Baugh Wooley's. The tree multiplier, based on our new PP units, achieved 15.4% and 9.4% reduction in power consumption and transistor counts compared to Wallace multiplier