Architecture Design of the H.264/AVC Encoder Based on Rate-Distortion Optimization

Abstract

Rate-distortion (RD) optimization (RDO) allows video encoders to achieve better compression efficiencies due to more reliable mode decisions. On the other hand, this technique involves a high computational cost when actual rates and distortions are estimated. To achieve real-time processing, video encoders apply simplified algorithms for mode decisions. This paper presents the H.264/Advanced Video Coding (AVC) encoder architecture, which benefits from the RDO and achieves high throughputs. To access actual motion vector predictors, the motion estimation is placed at the same macroblock stage as the RD mode analysis. The analysis is performed at the partition and macroblock levels. The reconstruction loop and the RDO modules have the high throughput of 32 samples/coefficients per clock cycle, which enables the analysis of a significant number of preselected candidate modes. The high-throughput simplified rate estimation introduces slight quality losses and supports both entropy coding methods available in H.264/AVC. The average quality for the two coding methods is decreased by 0.07 and 0.17 dB compared with the JM17 software using the RDO. The compression efficiency can be traded for throughput. The architecture is verified in the real-time FPGA hardware encoder. The synthesis results show that the architecture consumes 551k gates and 148.63-kB memories. It can support 1080p at 60 frames/s encoding for 90-nm TSMC technology.