Towards an FPGA-Based HEVC Encoder: A Low-Complexity Rate Distortion Scheme for AMVP

Abstract

Advanced motion vector prediction (AMVP) is a new technique adopted in the latest high efficiency video coding (HEVC) standard. AMVP block predicts an initial motion vector of the current block from a given set of candidates by means of rate distortion (RD) optimization process. Due to the large number of different-sized blocks, simplification of RD optimization process in AMVP block is highly appreciated. Therefore, we present a new RD optimization technique for AMVP block in HEVC encoder. The proposed RD calculation approach finds the best AMVP candidate by processing less number of feature pixels per every block. Experimental results show notable speedup in terms of AMVP processing time with tolerable quality degradation (PSNR) and bitrate requirement. The proposed RD calculation technique reduces the RD computational complexity of the AMVP block by 87.5% as maximum (i.e. 1.7% of the whole encoder complexity). This improvement is accompanied with a modest average PSNR loss of 0.10 dB and an increase by 2.4% in terms of bitrate. On the other hand, we present an FPGA-based architecture for AMVP unit in HEVC encoder. The proposed architecture was prototyped, simulated and synthesized on Xilinx Virtex-7 XC7VX550T FPGA. At 188 MHz clock frequency, the proposed architecture processes 8 K (7680 \(\times \) 4320) YCrCb resolution at 60 fps while utilizing less than 1% of the FPGA resources.