Abstract
In this paper we investigate and present the architecture design of a VLSI processor for Prolog based on the RISC concept. First the results of the analysis of several Prolog application programs are reported. Based on these results a reduced instruction set as well as the register and cache organisation of the Prolog RISC processor are presented. The evaluation of the performance of the Prolog RISC architecture shows that a performance comparable to those of complex sequential Prolog machines can be achieved.
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