Canonic Signed Digit Recoding based RISC Processor Design

Abstract

Objective: The objective of this work is to design a Reduced Instruction Set Computing (RISC) processor with Canonic Signed Digit (CSD) recoding. Methods: The incorporation of the CSD recording reduces the number of non-zero bits in the constant word length coefficient. The processor has a dedicated processing unit for the manipulation of floating point numbers. It uses CSD recoded number for the execution of the arithmetic operations such as multiplication. This novel technique reduces the switching activity and in turn resulting in reduction in the power consumed by the processor. Findings: The simulation was carried out using XILINX 14.3 and CADENCE NCLAUNCH. The RISC processor was synthesized with and without the CSD recoding. Although there is a slight increase in the area overhead, the use of ternary number representation in the processor design brought in a power reduction of 56.23%. Conclusions: The CSD recoding was found to be effective in terms of power consumption, making the RISC processor power efficient.