Application-Specific Arithmetic in High-Level Synthesis Tools

Yohann Uguen,Victor Lezaud,Steven Derrien,Florent De Dinechin

doi:10.1145/3377403

Abstract

This work studies hardware-specific optimization opportunities currently unexploited by high-level synthesis compilers. Some of these optimizations are specializations of floating-point operations that respect the usual semantics of the input program without changing the numerical result. Some other optimizations, locally triggered by the programmer thanks to a pragma, assume a different semantics, where floating-point code is interpreted as the specification of computation with real numbers. The compiler is then in charge to ensure an application-level accuracy constraint expressed in the pragma and has the freedom to use non-standard arithmetic hardware when more efficient. These two classes of optimizations are prototyped in the GeCoS source-to-source compiler and evaluated on the Polybench and EEMBC benchmark suites. Latency is reduced by up to 93%, and resource usage is reduced by up to 58%.

Highlights

Many case studies have demonstrated the potential of field-programmable gate arrays (FPGAs) as accelerators for a wide range of applications, from scientific and financial computing to signal and data processing, bioinformatics, molecular dynamics, stencil computations and cryptography [46]
One reason for the high development costs on FPGAs is that they inherited their programming model from digital circuit design
Results obtained with Vivado high-level synthesis (HLS) 2019.1 targeting Kintex7

Summary

Introduction

Many case studies have demonstrated the potential of field-programmable gate arrays (FPGAs) as accelerators for a wide range of applications, from scientific and financial computing to signal and data processing, bioinformatics, molecular dynamics, stencil computations and cryptography [46]. 5:2 von Neumann computing: dataflow operation without the need of instruction decoding; massive register and memory bandwidth without contention on a register file and single memory bus; and operators and storage elements tailored to the application in nature, number, and size. To unleash this potential, development costs for FPGAs are orders of magnitude higher than classical programming. The hardware description languages (HDLs) used have a very different programming paradigm than the languages used for software design. One can use software execution on a processor for simulation All of this drastically reduces development time

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Conclusion