Application of Junctionless Nanowire Transistor in the Self-Cascode Configuration to Improve the Analog Performance

Abstract

The self-cascode (SC) configuration consists in a series association of two transistors with tied gates usually applied to improve the analog performance of MOS devices. This paper compares the analog parameters of single Junctionless transistors with the ones presented by self-cascode associations composed by two Junctionless devices with identical or different fin widths (symmetric and asymmetric, respectively). The transconductance to the drain current ratio, the Early voltage (V EA ) and the intrinsic voltage gain (A V ) have been evaluated for both single devices and SC structures. It has been shown that the SC configurations, specially the asymmetric ones, present a strong reduction of the drain conductance (g D ) with respect to single devices, resulting in an increase of V EA and A V , which can be higher than 30 dB depending on the bias conditions.