Abstract
ABSTRACT This study reports the findings from an investigation into charge carrier transport within a silicon nanowire layer. The samples were prepared using the metal-assisted chemical etching method applied to crystalline silicon wafers with a resistance of 10–20 Ω·cm. The resulting silicon nanowires had a diameter of about 100 nm with a resistance of approximately 15 kΩ·cm. Electrical conductivity measurements were performed in both planar and sandwich configurations, revealing analogous conductivity mechanisms across different geometries. Frequency-dependent conductivity studies unveiled the presence of hopping conductivity. A hypothesis is proposed regarding the existence of a potential barrier at the interface between the nanowire layer and the substrate.
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