Analytical thermal model for multilevel VLSI interconnects incorporating via effect

Abstract

The authors present compact analytical thermal models for estimating the temperature rise of multilevel VLSI interconnect lines incorporating via effect. The impact of vias has been modeled using (1) a characteristic thermal length and (2) an effective thermal conductivity of ILD (interlayer dielectric), k/sub ILD,eff/, with k/sub ILD/,/sub eff/=k/sub ILD//spl eta//, where /spl eta/ is a physical correction factor, with 0</spl eta/<1. Both the spatial temperature profile along the metal lines and their average temperature rise can be easily obtained using these models. The predicted temperature profiles are shown to be in excellent agreement with the three-dimensional (3-D) finite element thermal simulation results. The model is then applied to estimate the temperature rise of densely packed multilevel interconnects. It is shown that for multilevel interconnect arrays, via density along the lines can significantly affect the temperature rise of such interconnect structures.