Analytical models for n/sup +/-p/sup +/ double-gate SOI MOSFET's

Abstract

Previously, we proposed n/sup +/-p/sup +/ double-gate SOI MOSFET's, which have n/sup +/ polysilicon for the back gate and p/sup +/ polysilicon for the front gate to enable adjustment of the threshold voltage, and demonstrated high speed operation. In this paper, we establish analytical models for this device, This transistor has two threshold voltages related to n/sup +/ and p/sup +/ polysilicon gates: V/sub th1/ and V/sub th2/, respectively. V/sub th1/ is a function of the gate oxide thickness t/sub Ox/ and SOI thickness t/sub Si/ and is about 0.25 V when t/sub Ox//t/sub Si/=5, while V/sub th2/ is insensitive to t/sub Ox/ and t/sub Si/ and is about 1 V. We also derive models for conduction charge and drain current and verified their validity by numerical analysis. Furthermore, we establish a scaling theory unique to the device, and show how to design the device parameters with decreasing gate length. We show numerically that we can design sub 0.1 /spl mu/m gate length devices with an an appropriate threshold voltage and an ideal subthreshold swing. >