15 ps cryogenic operation of 0.19-μm-LG n+- p+double-gate SOI CMOS

Abstract

We demonstrated a CMOS invertor with a 15 ps propagation delay (t<SUB>pd</SUB>) at 77 K. This device uses n<SUP>+</SUP> - p<SUP>+</SUP> double-gate SOI MOSFETs with a gate length (L<SUB>G</SUB>) of 0.19 micrometers and a gate oxide thickness (t<SUB>ox</SUB>) around 9 nm. The channel doping concentration of this device is maintained as low as 10<SUP>15</SUP> cm<SUP>-3</SUP> even in the deep submicron gate length regime while maintaining short channel immunity. Therefore, the decreased phonon scattering due to the cryogenic operation causes a significant increase in mobility, which leads to smaller t<SUB>pd</SUB> than any other reported values for a given L<SUB>G</SUB>. Although the threshold voltage (V<SUB>th</SUB>) increases with a decrease in temperature, we can adjust it for cryogenic operation by controlling t<SUB>ox</SUB> and the SOI thicknesses (t<SUB>Si</SUB>).