Modeling off-state leakage current of DG-SOI MOSFETs for low-voltage design

Abstract

The Double-Gate (DG) SOI MOSFETs have generated substantial attention because of ideal subthreshold swing, high transconductance, and excellent short-channel effect. These merits make DG-SOI MOSFETs one of the candidates for low-power CMOS technology. However, off-state subthreshold leakage current is a major design challenge for this type of device, especially when V/sub th/ is scaled down to very low value (<0.3 V). An accurate model of the off-state leakage current is very important to technology projection and low-voltage device design. An analytical model of the off-state leakage current for DG SOI MOSFETs was proposed based on the drift-diffusion theory and the 2D channel potential along the Si-film center path. The model agrees well with the measured data. Implications were obtained from technology projection for low-voltage device design.