Analytical modeling and simulation of a triple metal vertical TFET with hetero-junction gate stack

Abstract

In this paper, a new 2D analytical model for surface potential of a gate stacked triple metal Vertical TFET with n + delta doped layer (δ-doped n + SiGe GS-TMG-VTFET) is presented. The parabolic approximation process is used to solve the Poisson equation in terms of channel surface potential and electrical field respectively. The proposed method consists of a dual modulation effect that controls the surface potential at both the interface of the source and drains with the channel. This structure comprises SiO2 and HfO2 as gate-stacked materials to extend the control of the gate terminal over the channel. In addition, the proposed TMG-VTFET outperforms the surface potential results in terms of input and output characteristics like gate-source voltage (VGS) and drain-source voltage (VDS), gate oxide, and SiGe mole fraction. Finally, we obtained the expression of the channel surface potential, which involves the biasing variation of source and drain terminal. Our proposed model is accounting the variable of kane model in respect to extract the drain current characteristics. It can be modeled by integrating band-to-band tunneling generation rate using suitable boundary conditions. Now, efficiency of the proposed model for both the surface potential and drain current has been confirmed by comparing its analytical outcomes with the TCAD results.