Analytical drain current model to study the impact of negative capacitance phenomenon in Symmetric Double Gate Junctionless Transistor

Abstract

We have developed a complete drain current model to study the impact of negative capacitance phenomenon exhibited by ferroelectric materials in Symmetric Double Gate Junctionless Transistor using Pao-Sah current formulation and Landau Devonshire theory. Strontium Bismuth Tantalate (SBT) is used as gate insulator and no interface layer is considered in the analysis i.e. metal-ferroelectric-semiconductor (MFS) structure has been studied. Using the analytical model the various parameters obtained are gain, gate capacitance, subthreshold swing, threshold voltage, mobile charge density and drain current. It has been observed that values of gain>1 and subthreshold swing<60mV/dec can be achieved, thereby, signifying that device has suitability for faster, energy efficient switching applications.