Analytic I–V Model for Single-Electron Transistors

Xiaohui Wang,Wolfgang Porod

doi:10.1155/2001/71879

Abstract

We present an analytical model for the I–V characteristics of a single-electron transistor, which may be incorporated in a conventional circuit simulator, such as SPICE. Our model takes as its input the physical SET characteristics (capacitances and tunnel resistances, which may be determined experimentally), and it yields I–V curves which are in excellent agreement with the ones obtained from full-scale Monte Carlo simulations.

Highlights

Single-electron transistors (SET) offer the promise of ultra-high integration densities and ultra-low power consumption [1]
We present an analytical model for the I- V characteristics of a single-electron transistor, which may be incorporated in a conventional circuit simulator, such as SPICE
We present an analytical model for the I-V characteristics of a single-electron transistor, which may be incorporated in a conventional circuit simulator, such as SPICE

Summary

INTRODUCTION

Single-electron transistors (SET) offer the promise of ultra-high integration densities and ultra-low power consumption [1]. Source and drain junctions, and these tunneling rates la are given by the "orthodox theory" of single-electron tunneling. Current across the SET may be viewed as the combined process of an electron tunneling first across the source- and the drain junction (with rates las and lad respectively). Where the rates (within the "orthodox theory") are analytic functions of the SET parameters and the applied biases, Va and Vgs. the rates given by the changes in energy which can be expressed as junction charges in the following way: AEs e. C is the sum of all capacitances and Q0 represents some background charge This model is valid a long as the central island has one extra electron, i.e., the one that carries the current. More details can be found in a forthcoming publication [7]

RESULTS

SUMMARY