Analysis on performances of ultra-thin vertical MOSFET depending on position of gate-drain misalignment

Abstract

Abstract In this work, a series of technology computer-aided design (TCAD) device simulations have been carried out to investigate the effects of gate underlap and overlap structures on device performances of vertical-channel MOSFET. The device characterizations were conducted in both aspects of DC and high-frequency operations for higher completeness of this work since both are not usually optimized at the same time under the same structural and processing conditions. Under the underlap condition, slight degradation in the on-state current Ion drivability was observed. A noticeable off-state current Ioff increases were witnessed under the underlap conduction. It is explicitly demonstrated that excessive gate underlap results in non-ideal effects including degradation of subthreshold swing (S), worsening of drain-induced barrier lowering (DIBL), lowering of maximum transconductance (gm,Max). Although fT and fmax were sustained to be high under overlap and gate-drain alignment conditions,