Analytical potential distribution model of symmetric double gate underlap MOSFET with binary metal alloy as gate electrode for subdued sces

Abstract

In this work, we have used the novel concept of linearly graded binary alloy, as gate material in the popular structure of underlap symmetric Double Gate (DG) MOSFET and developed an analytical model to study the potential distribution in the gate overlap and underlap of our proposed structure. Based on this potential model, an overall performance comparison of the underlap DG MOS with and without work function engineered gate material have been carried out and the results obtained prove the fact that our proposed work function engineered gate underlap DG MOS lowers the potential minima to a further extent and is therefore more effective in subduing the various short channel effects (SCEs) and can provide better immunity against Drain Induced Barrier Lowering (DIBL). The lowering of potential minima with our proposed structure implies that the device is expected to show a lower threshold voltage, thereby increasing the current drivability and offering higher switching speed.