Analysis of the Performance of an Inverter Circuit: Varying the Thickness of the Active Layer in Polymer Thin Film Transistors with Circuit Simulation

Abstract

In this paper, we study, through simulation, the effects on the behavior of an inverter circuit when the active layer thickness of the polymer thin film transistor design is modified. A previously developed compact model for polymer transistors was implemented in standardized hardware description language. We validate results with measured characteristics of transistors fabricated with a poly(methyl methacrylate) layer on top of a poly(3-hexylthiophene-2,5-diyl). This analysis indicates that decreasing the thickness of the active layer can increase the output voltage swing and hence the noise margin in digital circuits. Higher noise margin and larger gain were found for inverters with active layer thicknesses less than 40 nm.