Analysis of Temperature Effect in Quadruple Gate Nano-scale FinFET

Abstract

Quadruple gate FinFET is a promising candidate among other multi-gate MOS devices due to it’s better scalability and higher short channel effect suppression capability in advanced technology node. In this work, we report the effect of temperature on various performance metrics of quadruple gate FinFET like electrostatic integrity, carrier mobility, switching ratio, analog/RF, and linearity parameters with the help of well-calibrated numerical device simulation-based study (TCAD). While increasing the temperature from 250 °K to 450 °K, due to the enhanced bulk phonon scattering, degradation in carrier effective mobility is observed. Sub-threshold swing and drain induced barrier lowering coefficient vary linearly with temperature. At high temperature, due to the reduced carrier mobility, degradation in the analog figure of merits is observed. RF performance parameters also degrade primarily due to the enhanced gate capacitance and reduced trans-conductance. However, some linearity parameter improves at high temperature due to the reduced magnitude of the higher-order derivative of trans-conductance. Another major contribution of this work is, we demonstrate the inflection point or temperature compensation point in some analog/RF performance metrics where the device characteristics almost invariant with temperature.