Analysis of Subthreshold Leakage Current in IP3 SRAM Bit-Cell under Temperature Variations in Deep-Submicrometer CMOS Technology

Abstract

In this paper, we present the analysis of subthreshold leakage current with temperature variations in an IP3 SRAM bit-cell. A comparison of subthreshold leakage current of IP3 SRAM bit-cell with conventional 6T, P4 and P3 is performed at elevated temperatures ranging from 0C to 125C. It is observed that subthreshold leakage increases with temperature and also IP3 SRAM bit-cell has the lowest subthreshold leakage variations when compared with conventional 6T , P4 and P3 SRAM bit-cell structures.