Analysis of MOSFET density and reduction in power consumption of Carry Select Adder using gate diffusion input

Abstract

The level of integration keeps on emerging which results in more and more complicated signal processors to be incorporated on a single chip. The applications of signal processing not just require huge computation ability but also consume substantial amount of energy. While performance remains to be the chief design toll, reduction in consumption of power has become an alarming area of consideration in today's VLSI system designs. The want for low-power VLSI systems and reduced area arouse the need to fabricate a Carry Select Adder (CSA) using different designing techniques. This paper approaches the designing of CSA using BEC-1 and also with GDI enabled D-latch implemented through Tanner tool. Consumption of power and density of MOSFETs are being compared and analysis of efficient CSA has been done.