Analysis of High-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> Spacer Asymmetric Underlap DG-MOSFET for SOC Application

Abstract

In this paper, asymmetric underlap double-gate (AUDG) MOSFET is studied to analyze the influence of high- $k$ spacer on the intrinsic device parameters. The AUDG-MOSFET architecture offers better device performance, particularly, drain-induced barrier lowering in contrast to the conventional double-gate (DG)-MOSFET. However, the ON current and the distributed resistances for the device increase considerably. The analysis of the device presented here shows that the detrimental effects of the device can be effectively eliminated using high- $k$ spacers. To evaluate the device performance and to study the improvement associated with the use of high- $k$ spacers, different intrinsic parameters are analyzed. These parameters include transconductance ( $g_{m})$ , transconductance generation factor ( $g_{m}$ / $I_{d})$ , intrinsic gain ( $g_{m}r_{o})$ , intrinsic capacitance ( $C_{\rm gd}$ , $C_{\rm gs})$ , resistance ( $R_{\rm gd}$ , $R_{\rm gs})$ , transport delay ( $\tau _{m})$ , inductance ( $L_{\rm sd})$ , cutoff frequency ( $f_{T}\!)$ , and the maximum frequency of oscillation ( $f_{\rm {max}})$ , gain bandwidth product, and inverter delay.