Analysis of enhanced hot-carrier effects in scaled flash memory devices

Abstract

In this paper, we analyze the impact of both junction scaling and channel length scaling on hot-carrier reliability of Flash memory devices with the help of a newly developed charge pumping technique. Lateral profiles of dopant concentration and erase-induced damage near both graded and abrupt junctions were obtained from charge pumping measurements. We found that more erase-induced damage is spread into the channel if the junction Is more abrupt. Further current-voltage (I-V) measurements and write/erase cycling experiments demonstrate that the effect of erase-induced damage on V/sub t/ becomes more severe when channel length is scaled down. To scale down Flash memory devices without sacrificing reliability, we suggest to either keep the source junction sufficiently graded or reduce the erase source bias.