Analysis of encapsulation process in 3D stacked chips with different microbump array

Abstract

This paper presented the study of encapsulation process in 3D stacked chips with different microbump arrays. An experiment was carried out on two-stacked chips with bumps in perimeter array, and validated with numerical simulation done in FLUENT 6.3. In the numerical study, three different microbump arrays, namely full, semi-full and perimeter arrays, were studied. It was found that perimeter array provided the easiest route for epoxy molding compound (EMC) flow front advancement with the least EMC conversion and microbump impediment. Therefore, the air entrapment level was the lowest in perimeter array. For full and semi-full arrays, higher level of air entrapment was observed as there were more significant EMC conversion, microbump impediment and imbalanced EMC flow fronts. The data presentation in this paper provides a good understanding on EMC flow behavior, especially in various microbump arrays during the encapsulation process.