Analysis of Electrical Parameters of Ge/Si Heterojunction GeOI FinFETs

Abstract

This paper proposes for the first time three heterojunction structures of FinFET, each structurally different from the other. The first structure is a heterojunction FinFET with Germanium fin, dual gate material and dual gate dielectric, where a Silicon layer near the source end creates a heterojunction. The second structure is a modification of the first one with the Silicon layer placed near the source and drain ends. The second structure further modifies into the third with the introduction of a gate-drain underlap. The third heterojunction FinFET having a gate-drain underlap on the drain shows the improved ION/IOFF and low leakage current compared to the other two structures. Therefore, a further detailed analysis is done for the third geometry, that is, dual gate material dual dielectric gate-drain underlap heterojunction FinFET. Analysis of the transfer characteristics are carried out for this structure for variations in gate-drain underlap length, concentration of both Silicon layers on source and drain ends, and fin width.