Abstract
In this study, the authors evaluate different schemes of address decoders based on bulk, single gate (SG) silicon-on-insulator (SOI) and double gate (DG) FinFET technology. Schemes differ in terms of back gate connections, and swing on the enable and address lines. The analysis for delay, power dissipation and critical charge has been carried out. Radiation induced single event transients and multiple bit upsets in address decoder have been studied. For radiation hardened applications, tied gate configuration has been found to be good choice over bulk, SG-SOI and independent gate configurations. The effect of process parameter variations on different schemes has been studied. HSPICE simulations have been performed with 45 nm bulk, SG-SOI and DG-FinFET predictive technology models.
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