Analysis and Optimization of Stability for 6T SRAM Cell Using 180 nm Technology

Abstract

This paper presents a simple circuit design of 6Transistor SRAM. This work is focused on an important parameter of any memory device known as stability. The 6T SRAM cell is simulated to improve stability. This paper focuses on two techniques for analysis of stability: trial and error technique and graphical technique for SNM calculation. SNM is the measure of stability. The analysis of stability is done on different ratios of W access and W driver transistor and on different supply voltages. Simulation is done using a 180 nm technology and different power supplies. Simulated results have important implications in the design of low-power SRAM.