Analysis and Design of Low Voltage Low Noise LVDS Receiver

Abstract

The relative advancement of technologies and availability of high frequency clocks and digital circuits, the operating frequencies of integrated circuits are increasing at a faster rate. But the rate at which different ICs communicate is not growing. So it requires an extremely high-performance solution that consumes a minimum power and is relatively immune to noise and inexpensive. Low Voltage Differential Signaling (LVDS) is a way to communicate data using a very low voltage swing (about 350mV) differentially over two PCB traces. It deals about the analysis and design of a low power, low noise and high speed comparator for a high performance Low Voltage Differential Signaling (LVDS) Receiver. The circuit of a Conventional Double Tail Latch Type Comparator is modified for the purpose of low-power and low noise operation even in small supply voltages. The circuit is simulated with 2V DC supply voltage, 350mV 500MHz sinusoidal input and 1GHz clock frequency. LVDS Receiver using comparator as its second stage is designed and simulated in Cadence Virtuoso Analog Design Environment using GPDK 180nm .By this design, the power dissipation, delay and noise can be reduced.