Analysis and Design of Low Voltage Low Noise LVDS Receiver

Bincy P Chacko, ,Christo Ananth

doi:10.9790/2834-09251018

Abstract

The relative advancement of technologies and availability of high frequency clocks and digital circuits, the operating frequencies of integrated circuits are increasing at a faster rate. But the rate at which different ICs communicate is not growing. So it requires an extremely high-performance solution that consumes a minimum power and is relatively immune to noise and inexpensive. Low Voltage Differential Signaling (LVDS) is a way to communicate data using a very low voltage swing (about 350mV) differentially over two PCB traces. It deals about the analysis and design of a low power, low noise and high speed comparator for a high performance Low Voltage Differential Signaling (LVDS) Receiver. The circuit of a Conventional Double Tail Latch Type Comparator is modified for the purpose of low-power and low noise operation even in small supply voltages. The circuit is simulated with 2V DC supply voltage, 350mV 500MHz sinusoidal input and 1GHz clock frequency. LVDS Receiver using comparator as its second stage is designed and simulated in Cadence Virtuoso Analog Design Environment using GPDK 180nm .By this design, the power dissipation, delay and noise can be reduced. Index Terms: Double-tail comparator, Buffer, Differential Amplifier

Highlights

The past few decades have witnessed introduction of new technologies
Low voltage differential signaling (LVDS) is a technology-independent input-output standard used for data communications, telecommunications, etc. where high speed data transfer is necessary
Low Voltage Differential Signaling (LVDS) is developed for low voltage, low power, low noise and high speed IO interfaces

Summary

Introduction

The past few decades have witnessed introduction of new technologies. The scaling of CMOS Technology and high level silicon integration tends to increase the on-chip data rates. Current-Mode Logic (CML) and Low-Voltage Positive-Emitter-Coupled Logic (LVPECL) are the commonly used techniques for high speed data transmission at a rate of 10Gbps. These techniques require an input signal swing of 800 mV and consume more power during data transmission. Low voltage differential signaling (LVDS) is a technology-independent input-output standard used for data communications, telecommunications, etc. LVDS is developed for low voltage, low power, low noise and high speed IO interfaces. It uses a small swing differential signal of 350mV for fast data transfer at significantly reduced power and excellent noise immunity. Compared to other differential cable driving standards like RS422 and RS485, LVDS has the lowest differential swing

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