Analysis and design of low power radix-4 FFT processor using pipelined architecture

Abstract

Fast Fourier Transform is an elevated form of Discrete Fourier Transform which is much simpler, effective, and faster with lesser number of computations has dominated in various fields. As the gate length of CMOS is going deeper and deeper into Ultra Deep Sub-Micron (UDSM) the leakage power which was negligible before is tending towards the dynamic power range, increasing the requirement of low power devices. This paper presents several low power techniques like sign swap, sub expression elimination along with several area reduction techniques like “In Place” addressing, single butterfly element per stage using the pipelined architecture. In this paper pipelined architecture with low power techniques is implemented on both radix-2 and radix-4 FFT processor and compared. Results shows that pipelined Radix-4 FFT consumes 11% less power compared to radix-2 FFT for 16 point implementation.