Abstract
In this paper, a novel design of Multi-Path Delay Commutator Architecture FFT processor(MDC-FFT) is proposed based on customized rotation factor ROM(RF-ROM) with various memory access mechanism for OFDM systems. For the OFDM systems, the combined FFT algorithm of Radix-2 FFT and Radix-22FFT is conducted. The pipeline architecture is also proposed for its high throughput and scalability. With hybrid FFT algorithm using optimized RF-ROM, the storage size of rotation factor is efficiently reduced. The proposed architecture has been synthesized on the FPGA platforms. Experimental results show that the proposed MDC-FFT processor works on the maximum clock frequency of 150MHz and can realize 128/256/512/1024/2048/4096 point FFT. With proper hardware resources, the longest symbol processing time is 40.635µs, which satisfy the LTE-A standard and performs 5%~46.8% better than other architectures.
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