Hardware Implementation of Pipelined FFT using Polyphase Decomposition

Abstract

FFT is the fundamental unit of any signal processing system. Performance characteristics like speed, computational complexity and power consumption are dependent on FFT calculation. Optimizing FFT algorithm plays a significant role in optimizing the signal processing system. Hardware implementation of FFT follows a strict mathematical sense and hence has many problems with its VLSI realization. This paper presents the implementation of FFT algorithm based on pipeline architecture using the polyphase decomposition concept. The proposed architecture is designed to reduce the computational complexity and at the same time not compromising the speed of the overall DSP system. Polyphase decomposition is used to segment the long input sequence into P sub sequences by using decimation factor ‘P’. The FFT of these segmented sequences is computed serially by using pipelined Radix-2 MDC architecture with higher throughput rate. Finally, results are combined to get complete FFT of original sequence by using (P-1) adders and multipliers. In addition to this, the proposed architecture also allows the calculation of any “even-length” point FFT within a specified range which depends on the decimating factor. The computational complexity is reduced by a large factor when compared with the existing FFT algorithms. The use of MDC architecture ensures higher throughput compared to other existing architectures. The proposed architecture is more efficient than existing in terms of throughput rate and maximum clock frequency.