An unsigned truncated sequential multiplier with variable error compensation

Abstract

Estimating arithmetic deals with trading accuracy for speed, silicon area, and/or power consumption. Truncated parallel multipliers, which reduce power and area approximately by half, are very important units in estimating arithmetic. An n-bit unsigned truncated sequential multiplier with new approaches that compensate for the truncation error is proposed in this paper. These compensating approaches improve the result accuracy using the (n−1)th or nth columns of the partial product matrix dynamically. By introducing a small circuit into the original sequential multiplier, these approaches compensate for the error resulting from removing the carry bits of the least significant parts of the partial product matrix. The maximum relative error of the new truncated multiplier is approximately 2.03%, thus it is only slightly different from that of the precise counterpart in terms of accuracy. A timing evaluation is conducted for the critical path of the proposed multiplier, applying a pre-layout logical synthesis. The evaluation reveals that depending on the operands length, this proposed multiplier is approximately 2.5% to 26.6% faster than the precise multiplier.