An unlimited lock range DLL for clock generator

Abstract

Listen

Translate article

In this paper, we design a wide range DLL (Delay Locked Loop) for a clock generator. A DLL-based clock generator has several inherent advantages over conventional PLL-based clock generators, such as no noise accumulation, fast lock and loop stability (1-st order loop filter). We propose a new DLL architecture to overcome a limited lock range. The proposed DLL is fabricated in a 0.25-/spl mu/m n-well CMOS technology and an unlimited lock range is achieved. It operates in a reference signal of 5 MHz to 100 MHz, occupies 480/spl times/160 /spl mu/m/sup 2/ and dissipates only 5.8 mW to generate 16-delayed clocks at 100 MHz reference signal. It has only /spl plusmn/0.5% peak-to-peak jitters.