A novel 14 ∼ 170 MHz All digital delay locked loop with ultra fast locking for SoC applications

Abstract

A delay locked loop (DLL) is a feedback control system that equalizes the phase of two delayed copies of the same clock signal. The DLL is useful for compensating the clock distribution delays that arise in many system configurations. An all-digital delay-locked loop (ADDLL) is presented to achieve wide range of operation, fast lock, Harmonic-Free and process immunity. The paper proposes a Modified Variable Successive Approximation Register-controlled (MVSAR) algorithm to achieve the fast-locking property, closed-loop operation and performing binary search without harmonic-locking issue. The fast locking of proposed MVSAR is verified by comparing it with the existing architectures. The proposed ADDLL is implemented at system level with standard cells and it has good portability over different processes. It is synthesized using TSMC 0.18µm, six-metal technology. The lock range (operating frequency range) of the ADDLL is 14MHz to 170 MHz and occupied an area (physical design) of 142*142 Sq.µm (0.020164 Sq.mm).