An Ultra-Low-Power Process-and- Temperature Compensated Ring Oscillator

Abstract

The need for low-power and high-precision clock is desirable for systems that target high power efficiency. In most designs, a complex compensation technique is required to generate a Process-Voltage-Temperature (PVT) independent clock which has a high-power consumption power and occupies a large silicon area. This paper presents the design of a 3-stage current-starved ring oscillator that compensates for process and temperature variations. The proposed ring oscillator achieves up to 90% reduction in the frequency variation from its center frequency across process and temperature variations compared to the conventional current-starved ring oscillator. The proposed design is implemented in a standard 130-nm CMOS process. The power for the proposed circuitry is 346 nW and occupies an area of 315 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .