Abstract
A 3-stage current-starved ring oscillator with 65.1% reduction in process variation in a 90nm CMOS process is presented. The low variation is achieved without degrading the mean operating frequency through the implementation of an addition-based current source to replace a single transistor current source in each inverter stage. No post-fabrication trimming or calibration is required. Circuit simulations indicate that the proposed circuitry is well suited for scaling beyond 90nm. Measurements that are taken from 2 separate wafers and 167 test chips show 65.1% less process variation in output frequency, compared to a conventional current-starved ring oscillator. The power overhead for the additional circuitry is 33µW.
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