An ultralow on-resistance high-voltage SOI p-channel LDMOS

Abstract

A novel SOI pLDMOSFET with ultralow specific on-resistance (Ron,sp) is proposed and investigated by simulation. It features an Accumulation-mode Gate (AG) directly extending to the drain over the P-type drift region (called AG pLDMOS). The AG consists of a linearly doped N-region and two back-to-back diodes. In the on-state, the AG makes major-carrier holes accumulate along the drift region surface. The accumulation layer provides an ultralow-resistance current path, and thus significantly reduces the Ron,sp. In the off-state, the AG modulates the surface electric field distribution to improve the breakdown voltage (BV); Moreover, the N-region in the AG assists in depleting the P-type drift region, and thus increases the doping concentration of the drift region (Nd) and further reduces the Ron,sp. The two back-to-back diodes are employed to sustain high voltage between the gate and drain in the on-state and off-state, respectively. As a result, the AG pLDMOS not only improves the tradeoff between the BV and Ron,sp, but also makes the Ron,sp almost independent of the Nd. Compared with the conventional SOI pLDMOS, the AG pLDMOS reduces the Ron,sp by 74.6% and increases the BV from 221 V to 319 V.