Ultralow ON-Resistance High-Voltage p-Channel LDMOS With an Accumulation-Effect Extended Gate

Abstract

The high ON-resistance and the limited breakdown voltage (BV) are the two major issues for the p-channel lateral double-diffused MOSFET (pLDMOS). To solve the two issues, an ultralow specific ON-resistance ( $R_{\mathrm{\scriptscriptstyle ON},\textrm {sp}}$ ) pLDMOS with improved BV is proposed and investigated by simulation. It features an extended gate (EG) with accumulation effect over the drift region and a P+ floating layer (PFL) in the N-sub. In the ON-state, the EG induces the hole accumulation layer along the drift region surface, providing an ultralow-resistance conducting path. This accumulation-type current transport mode makes $R_{\mathrm{\scriptscriptstyle ON},\textrm {sp}}$ almost independent of the drift region doping concentration ( $N_{d}$ ) and contributes to a much lower $R_{\mathrm{\scriptscriptstyle ON},\textrm {sp}}$ , which greatly breaks through the silicon limit of $R_{\mathrm{\scriptscriptstyle ON},\textrm {sp}}\propto \textrm {BV}^{2.5}$ . In the OFF-state, the EG not only modulates the surface electric field ( $E$ -field) distribution to enhance the BV, but also helps deplete the drift region to increase the optimized $N_{d}$ , and thus further reduce $R_{\mathrm{\scriptscriptstyle ON},\textrm {sp}}$ . Moreover, the PFL is not depleted, and thus equipotential in the lateral direction. Therefore, the PFL not only modulates the bulk $E$ -field distribution at the source and drain sides but also introduces an additional vertical diode to sustain a higher BV. Owing to the effects mentioned above, the simulated results show that the EG PFL pLDMOS decreases $R_{\mathrm{\scriptscriptstyle ON},\textrm {sp}}$ by 68% and increases the BV by 47% compared with the conventional pLDMOS.