Ultralow ON-Resistance SOI LDMOS With Three Separated Gates and High-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math> </inline-formula> Dielectric

Abstract

A novel ultralow specific on-resistance ( $R_{\mathrm{\scriptscriptstyle ON},\text {sp}})$ SOI lateral double-diffused MOS (LDMOS) with three separated gates (TSGs) and high- $k$ (HK) pillars is proposed and investigated by simulation. The TSGs include the planar gate ( $G_{X}$ ), the segmented trench gate ( $G_{Y})$ between the p+ body contact regions, and the embedded trench gate ( $G_{Z}$ ) connected with HK pillars and p-well regions. First, in the on-state, the TSGs form three channels, including one lateral channel and two vertical channels, which can decrease $R_{\mathrm{\scriptscriptstyle ON},\text {sp}}$ significantly. Second, $G_{Y}$ and $G_{Z}$ are extended to the buried oxide, widening the vertical conduction area and enhancing the current density in the bulk to further reduce $R_{\mathrm{\scriptscriptstyle ON},\text {sp}}$ . Furthermore, the electron accumulation layer (EAL) is formed not only beside the extended $G_{Y}$ and $G_{Z}$ , but also along the sidewall of the drift region near the source side, thus reducing $R_{\mathrm{\scriptscriptstyle ON},\text {sp}}$ greatly. Third, the HK pillars can increase the optimal drift doping concentration ( $N_{d})$ to decrease $R_{\mathrm{\scriptscriptstyle ON},{\mathrm{ sp}}}$ owing to the assisted depletion effect. The device obtains an ultralow $R_{\mathrm{\scriptscriptstyle ON},\text {sp}}$ of 0.34 $\text{m}\Omega \cdot {\mathrm{ cm}}^{2}$ at BV = 97 V. Compared with the conventional LDMOS and other previous devices, the TSG-HK LDMOS achieves better tradeoff between the breakdown voltage and $R_{\mathrm{\scriptscriptstyle ON},\text {sp}}$ .