An optimized 1.0- mu m CMOS technology for next-generation channelless gate arrays

Abstract

An optimized 5-V 1.0- mu m CMOS technology has been developed to achieve high speed and high packing density for channelless gate arrays. In addition to the downward scaling of CMOS device geometry, reduction of the parasitic resistances is essential for next-generation channelless gate arrays. The technology utilizes sidewalled PMOS and lightly doped drain (LDD) NMOS structures with 1.0- mu m actual physical gate lengths and 20-nm gate-oxide thickness. Tungsten metal is selectively deposited on the source and drain regions to reduce sheet resistivity, thus gaining extra speed improvement. This technology was applied to a large-scale gate array of over 40 K usable gates; high-speed (290-ps) operation has been achieved for a two-input NAND gate with a fan-out of 2. An advanced graphic processor with over 35 K used gates has been successfully demonstrated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>