Abstract
Pipelines, in Reduced Instruction Set Computer (RISC) microprocessors, are expected to provide increased throughputs in most cases. However, there are a few instructions, and therefore entire assembly language codes, that execute faster and hazard-free without pipelines. It is usual for the compilers to generate codes from high level description that are more suitable for the underlying hardware to maintain symmetry with respect to performance; this, however, is not always guaranteed. Therefore, instead of trying to optimize the description to suit the processor design, we try to determine the more suitable processor variant for the given code during compile time, and dynamically reconfigure the system accordingly. In doing so, however, we first need to classify each code according to its suitability to a different processor variant. The latter, in turn, gives us confidence in performance symmetry against various types of codes—this is the primary contribution of the proposed work. We first develop mathematical performance models of three conventional microprocessor designs, and propose a symmetry-improving nonlinear optimization method to achieve code-to-design mapping. Our analysis is based on four different architectures and 324,000 different assembly language codes, each with between 10 and 1000 instructions with different percentages of commonly seen instruction types. Our results suggest that in the sub-micron era, where execution time of each instruction is merely in a few nanoseconds, codes accumulating as low as 5% (or above) hazard causing instructions execute more swiftly on processors without pipelines.
Highlights
Reduced Instruction Set Computer [1], or RISC for short, has seen tremendous advancement over the last four decades
The performance limitations of the sym11070938 www.mdpi.com/journal/symmetryProcessor (SCP) were addressed in the advanced versions, which were based on multicycle execution of each instruction, and later followed by incorporation of pipelining, in which multiple instructions could be executed in parallel [6]
Please note that advancement in technology will lead to smaller execution times, x-axis on each plot may represent newer to older processors
Summary
Reduced Instruction Set Computer [1], or RISC for short, has seen tremendous advancement over the last four decades. The digital systems using the concept of DPR can be categorized into two: a static non reconfigurable part of the design, and runtime reconfigurable part. The former uses the generated full bit stream of the design downloaded into the system at boot time, whereas, the runtime reconfigurable part of the design may comprise several independent reconfiguration regions. These regions have a flexibility to be reconfigured in runtime by downloading the generated partial bit streams without affecting the functionality of the static non reconfigurable part [18]
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have