Dynamic Instruction Set Coprocessors

Abstract

A review of existing computers would reveal very powerful bit slice engines for specialized purposes and slower machines for general purposes. Reduced Instruction Set Computers (RISC) take up the middle ground in performance between the two, providing increased performance over the general-purpose machines at the cost of increased compilation time in order to use wasted cycles. This paper addresses the design, applications, and advantages of the Dynamic Instruction Set Coprocessor (DISC). The DISC can be used to provide processing speeds of up to 750 Million Instructions Per Second (MIPS) with existing technologies and to speed up certain software applications by several orders of magnitude. A DISC is similar to a RISC in that compilation time may increase by an order of magnitude in order to save several orders of magnitude in execution time. Likewise, a DISC goes beyond the hardware performance offered by today's bit slice engines, and will probably always achieve this because of its improved architecture and fewer internal gate delays. DISCs can be readily implemented from a circuit card size up to a bread box size or larger and require only standard cooling and power requirements. Multiple DISCs may be arranged for either a single instruction multiple data or a multiple instruction multiple data coprocessor capable of operating at an effective rate of 20 billion instructions per second or higher. This paper presents three different examples dealing with DISCs--one in the digital signal processing area, one in general purpose computing and one in radar signal processing.