An On-Line Timing Error Detection Method for Silicon Debug

Abstract

Error detection and locating during the post-silicon stage is a critical concern in modern IC industry. Especially timing errors caused by uncertain variations and electrical bugs are by far lacking effective methods to debug. In order to meet this challenge, we propose an on-line timing error detection method, which uses the on-chip storage to hold the golden execution trace by running the test program under the lower frequency condition, followed by comparison of the stored golden trace against runtime trace acquired under the specified test condition. Timing errors are founded after some differences appeared during the trace comparison. This self-checking approach can detect tricky timing errors without the time-consuming software simulation and trace dumping, which accelerates the detection procedure by orders of magnitude. Besides, tracing internal key signals will find timing errors as soon as the error occurs, which can decrease the latency of error detection. The experiments on FPGA show it is effective to detect timing errors for a core-based system on chip (SoC) design and speeds up the timing error debug process with less than 2% hardware cost.