An IP of an Advanced Encryption Standard for Altera" Devices

Abstract

This work presents an IP of the Rijndael Encryption algorithm, the new Advanced Encryption Standard (AES) approved by the National Institute of Standards and Technology (NIST). The IP uses a VHDL description optimized to Altera devices. This Rijndael implementation run it's symmetric cipher algorithm using a key with 128 bits. This mode is called AES128. Two designs are proposed. The first one is a performance version, using full parallel operation and achieving an 820Mbps throughput in an APEX device. The second and third designs present two costs x benefit approaches. The paper presents the Rijndael basics structures, the AES128 architecture and results of throughput and device utilization in Altera devices.