An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

Abstract

The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65 nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.